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Ȩ Ȩ > ¿¬±¸¹®Çå > ±¹³» ³í¹®Áö > Çѱ¹Á¤º¸°úÇÐȸ ³í¹®Áö > Á¤º¸°úÇÐȸ ³í¹®Áö C : ÄÄÇ»ÆÃÀÇ ½ÇÁ¦

Á¤º¸°úÇÐȸ ³í¹®Áö C : ÄÄÇ»ÆÃÀÇ ½ÇÁ¦

Current Result Document : 7 / 7 ÀÌÀü°Ç ÀÌÀü°Ç

ÇѱÛÁ¦¸ñ(Korean Title) WWCLOCK: Ç÷¡½Ã ¸Þ¸ð¸®ÀÇ ºñ´ëĪÀû ÀÔÃâ·Â ºñ¿ëÀ» °í·ÁÇÑ ÆäÀÌÁö ±³Ã¼ ¾Ë°í¸®Áò
¿µ¹®Á¦¸ñ(English Title) WWCLOCK: Page Replacement Algorithm Considering Asymmetric I/O Cost of Flash Memory
ÀúÀÚ(Author) ¹ÚÁؼ®   ÀÌÀºÁö   ¼­Çö¹Î   °í°Ç   Junseok Park   Eunji Lee   Hyunmin Seo   Kern Koh  
¿ø¹®¼ö·Ïó(Citation) VOL 15 NO. 12 PP. 0913 ~ 0917 (2009. 12)
Çѱ۳»¿ë
(Korean Abstract)
³½µå Ç÷¡½Ã ¸Þ¸ð¸®´Â Çϵåµð½ºÅ©¿Í ´Þ¸® Àбâ ÀÔÃâ·Â°ú ¾²±â ÀÔÃâ·ÂÀÌ ¼Ò¸ðÇÏ´Â ½Ã°£ ¹× Àü·Â·®ÀÌ ´Ù¸£¸ç ±× ºñÀ²Àº SLC, MLC, SSD µî ´Ù¾çÇÑ ÇüÅ¿¡ µû¶ó »óÀÌÇÏ´Ù. ƯÈ÷ ÃÖ±Ù¿¡´Â ³»Àå ¸Þ¸ð¸® ÀåÄ¡¿Í ÇÔ²² ¿ÜÀå ¸Þ¸ð¸® Ä«µå ¶Ç´Â USB ¸Þ¸ð¸®¸¦ µ¿½Ã¿¡ »ç¿ëÇÏ´Â °æ¿ìµµ Áõ°¡ÇÏ°í À־, ¹öÆÛ Ä³½Ã ±³Ã¼ ¾Ë°í¸®ÁòÀ» ¼³°èÇÏ´Â µ¥ À־ ÆäÀÌÁöÀÇ ÀçÂüÁ¶ È®·ü»Ó ¸¸ ¾Æ´Ï¶ó Á¢±Ù ÀåÄ¡¿Í ÂüÁ¶ Á¾·ù¿¡ µû¸¥ ÀÔÃâ·Â ºñ¿ëÀ» ÇÔ²² °í·ÁÇØ¾ß ÇÑ´Ù. º» ³í¹®Àº ÆäÀÌÁöÀÇ ÂüÁ¶ ºóµµ(frequency), ÃÖ±Ù¼º(recency) Á¤º¸¿Í ÇÔ²² Àбâ¿Í ¾²±âÀÇ ÀÔÃâ·Â ºñ¿ëÀ» Á÷Á¢ÀûÀ¸·Î °í·ÁÇÏ´Â WWCLOCK (Write-Weighted CLOCK) ¾Ë°í¸®ÁòÀ» Á¦¾ÈÇÑ´Ù. WWCLOCKÀº ÀÔÃâ·Â ºñ¿ëÀÌ ´Ù¸¥ ´Ù¾çÇÑ 2Â÷ ÀúÀåÀåÄ¡¿¡ ´ëÇØ Àû¿ë °¡´ÉÇϸç, CLOCK¿¡ °¡±î¿î ³·Àº ½Ã°£ ¹× °ø°£ º¹Àâµµ¸¦ °®°í ÀÖ´Ù. Æ®·¹À̽º ±â¹Ý ½Ã¹Ä·¹À̼ÇÀ» ÅëÇØ Á¦¾ÈµÈ ¾Ë°í¸®ÁòÀÌ LRU ¾Ë°í¸®Áò¿¡ ºñÇØ Àüü ÀÔÃâ·Â ½ÇÇà ½Ã°£À» Æò±Õ 36.2% °¨¼Ò½ÃÅ´À» º¸ÀδÙ.
¿µ¹®³»¿ë
(English Abstract)
Flash memories have asymmetric I/O costs for read and write in terms of latency and energy consumption. However, the ratio of these costs is dependent on the type of storage. Moreover, it is becoming more common to use two flash memories on a system as an internal memory and an external memory card. For this reason, buffer cache replacement algorithms should consider I/O costs of device as well as possibility of reference. This paper presents WWCLOCK(Write-Weighted CLOCK) algorithm which directly uses I/O costs of devices along with recency and frequency of cache blocks to selecting a victim to evict from the buffer cache. WWCLOCK can be used for wide range of storage devices with different I/O cost and for systems that are using two or more memory devices at the same time. In addition to this, it has low time and space complexity comparable to CLOCK algorithm. Trace-driven simulations show that the proposed algorithm reduces the total I/O time compared with LRU by 36.2% on average.
Å°¿öµå(Keyword) ¹öÆÛ Ä³½Ã ±³Ã¼ ¾Ë°í¸®Áò   ºñ¿ë ÀνĠ  À̱âÁ¾ ÀúÀåÀåÄ¡   Buffer Cache Replacement Algorithm   Cost-aware   Heterogeneous storage  
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